Joint Seminar hosted by Intel Research Pittsburgh/CALCM (Computer
Architecture Lab at Carnegie Mellon)

What: "Trading Off Cache Capacity for Reliability to Enable Low
Voltage Operation"

Who: Chris Wilkerson, Intel, Oregon Microarchitecture Lab

When: 4:30-5:30 PM    October 27, 2008

Where: Intel Research Pittsburgh Lounge (CIC building, 4th floor)


ABSTRACT

One of the most effective techniques to reduce power consumption is to
reduce supply voltage. However, reducing voltage in the context of
manufacturing-induced parameter variations can cause many types of
memory circuits to fail.  As a result, voltage scaling is limited by a
minimum voltage, often called Vccmin, beyond which memory circuits may
not operate reliably.  Large memory structures (e.g., caches)
typically set Vccmin for the whole processor.

In this paper, we describe two architectural techniques that enable
microprocessor caches (L1 and L2), to operate despite very high memory
cell failure rates.  As a result, we can substantially reduce Vccmin
for the cache structures, and allow low voltage operation for the
microprocessor as a whole.  Two main schemes are used to facilitate
such operation. The Word-disable scheme combines two consecutive cache
lines to form a single cache line where only non-failing words are
used. The Bit-fix scheme uses a quarter of the ways in a cache set to
store positions and fixing bits for failing bits in other ways of the
set.

During high voltage operation, at or above 825mV both schemes allow
use of the entire cache.  During low voltage operation, they sacrifice
cache capacity by 50% and 25%, respectively, to reduce Vccmin below
500mV. Compared to current designs with a Vccmin of 825mV, the word
disable scheme achieves this reduction in Vccmin in exchange for 50%
of lost cache capacity.  The Bit-fix scheme achieves a similar
reduction in Vccmin with a 25% capacity loss. Our schemes reduction in
Vccmin enables a 40% Vcc voltage reduction, which reduces power by 85%
and energy per instruction (EPI) by 535%.

SPEAKER BIO

Chris Wilkerson graduated from Carnegie Mellon University in 1996 with
a combined B.S./M.S. degree in ECE. Since then he has spent most of
his time working at Intel's research lab in Oregon.  Chris has
published a number of papers spanning several micro-architectural
topics including value prediction, branch prediction, cache
organization, run-ahead and advanced speculative execution.  Recently,
Chris has focused on low power design including micro architectural
mechanisms to enable low voltage operation for microprocessors.